The present invention generally relates to a row address generator for use in a memory system of the type incorporating a plurality of memory banks. The present invention more particularly relates to such an address generator, for use in a memory system including a plurality of dynamic random access memory banks and wherein one of the memory banks includes a memory device having an upper or lower half which is inoperative to assure that only the operative half of the memory device is addressed when its corresponding memory bank is accessed.
Memory systems are well known in the art. In applications where a large amount of memory space is required, such as in personal computer applications, memory systems may include more than one memory bank. Also, dynamic random access memories are extremely popular in such applications because of their extremely high memory density.
In a typical system, when a byte of data is to be stored, each memory bank is provided with the same memory address, first a row address, and then a column address. The particular memory location is selected with the application of first, a row address strobe signal and then a column strobe signal being applied to the proper memory bank. A write enable signal is then applied to each memory bank which is maintained as the byte of data is conveyed to each bank. Because only one bank is enabled to receive the row and column address, the byte of data is stored within its own unique storage location.
Dynamic random access memories are available in different types with each type corresponding to a respective different storage capacity. There are basically three different dynamic random access memory types, a 256KB type, a 1MB type, and a 4MB type. These different memory types afford flexibility to the ultimate user who may wish to tailor the storage size to a particular application or to increase the storage size of an existing system.
Each memory type requires a different type of access cycle. This is mainly due to the need for a different number of address bits for each type. For example, the 256KB type requires nine row and nine column address bits, the 1MB type requires ten row and ten column address bits, and the 4MB type requires eleven row and eleven column address bits.
Dynamic random access memories generally are divided in halves, an upper half and a lower half. Each half contains one-half of the total number of available storage locations. For example, in a 1MB type DRAM, the upper half will contain 512KB of memory space and the lower half will contain 512KB of memory space.
Often, defective dynamic random access memory devices will be fully operative in one half of the device and inoperative in the other half of the device. While only one half of a DRAM may be operative, it still can represent considerable memory space. For example, a 1MB DRAM which is operative only in the upper or lower half of the device can still provide 500KB of memory space. This is nearly twice as much memory space as is available in a 265KB memory.
Such defective DRAM's are commercially available and represent a considerable cost saving as compared to fully functional devices. Unfortunately, current memory systems are not able to accommodate such defective DRAM devices. More specifically, current memory systems are not able to assure that only the operative half of the defective device is addressed during accessing.